In the present age of high-speed computing and portable electronic devices, efforts are continuously made to reduce the size of devices without compromising on their computing speed. One of the preferred ways to achieve a reduction in the size is by reducing the size of transistors used in such devices.
Most of the electronic devices manufactured nowadays use metal oxide semiconductor field effect transistors (MOSFETs). MOSFETs (n-type or p-type) include a source region, a drain region, and a gate. Whenever voltage is applied across the source and drain regions and to the gate of the MOSFET, electrons flow from the source region to the drain region, resulting in the flow of current from the drain region to the source region.
In a typical MOSFET, the source region, the drain region, and the gate are laterally placed. In other words, the drain region is laterally adjacent to the gate of the MOSFET and the gate is laterally adjacent to the source region. This structure of the MOSFET has been in use for a number of years now. However, due to its lateral structure, it becomes challenging to reduce its size beyond a certain limit. Also, decreasing the size beyond a particular point often affects the performance of transistors, and hence the electronic device using them.
In light of the above observation, it is desirable to provide a transistor which is compact without reducing performance.